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integrated circuit systems, inc. ics951601 preliminary product preview 0663c?10/04/05 block diagram general purpose frequency timing generator recommended application: general purpose clock generator output features: 17 - pci clocks selectable, either 33.33mhz or 66.6mhz @ 3.3v 1 - 48mhz @ 3.3v 1 - ref @ 3.3v, 14.318mhz. features: programable spread spectrum precentage for emi control uses external 14.318mhz crystal select pins for frequency select pll2 pll1 spread spectrum 48mhz pci1a (7:0) pci2a (2:0) pci1b (2:0) pci2b (2:0) 8 3 3 3 x1 x2 xtal osc pci divder pci divder pci divder pci divder s data sclk sela (2:1) selb (2:1) spread control logic config. reg. ref0 power groups: vdda = analog power gnda = analog ground product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and o ther specifications are subject to change without notice. key specifications: pci ? pci output skew within same bank @ 33mhz: <170ps pci ? pci output skew within same bank@ 66mhz: <340ps cycle to cycle jitter pci @ 33mhz: <200ps cycle to cycle jitter pci @ 66mhz: <200ps cycle to cycle jitter 48mhz: <350ps cycle to cycle jitter ref: <500ps slew rate: 1.5 - 4 v/ns. (pci spec.) pin configuration 48-pin ssop *120k ohm pull-up to vdd on indicated inputs. ref0 vdd x1 x2 gnd sdata sclk gnda vdda sel1a pci1a_0 pci1a_1 vdd33 gnd pci1a_2 pci1a_3 gnd vdd33 pci1a_4 pci1a_5 vdd33 gnd pci1a_6 pci1a_7 48mhz gnd vdd48 spread vdda gnda sel2b pci2b_2 pci2b_1 gnd vdd66 pci2b_0 sel2a pci2a_2 pci2a_1 vdd2a gnd pci2a_0 sel1b pci1b_2 pci1b_1 gnd vdd1b pci1b_0 ics951601 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2 ics951601 preliminary product preview 0663c?10/04/05 pin descriptions pin number pin name type description 1 ref0 out reference output 2, 13, 18, 21, 26, 33, 38, 46 vdd pwr 3.3v power supply 3 x1 in crystal input,nominally 14.318mhz. 4 x2 out crystal output, nominally 14.318mhz. 9 , 44 vdda pwr analog 3.3v power supply 10, 30, 36, 42 selxx in real time pci output frequency selection pins 5, 14, 17, 22, 27, 32, 3 9 , 47 gnd pwr ground pins 6sdata i/o data pin for i 2 c circuitry 5v tolerant 7sclk in clock input of i 2 c input 8, 43 gnda pwr analog ground pins 24, 23, 20, 1 9 , 16, 15, 12, 11, pci1a (7:0) out pci clock outputs, selectable to be either 33.33 or 66.66mhz at 3.3v. 2 9 , 28, 25 pci1b (2:0) out pci clock outputs, selectable to be either 33.33 or 66.66mhz at 3.3v. 35, 34, 31 pci2a (2:0) out pci clock outputs, selectable to be either 33.33 or 66.66mhz at 3.3v. 41, 40, 37 pci2b (2:0) out pci clock outputs, selectable to be either 33.33 or 66.66mhz at 3.3v. 45 spread in enables spread spectrum, default is on. 48 48mhz out fixed 48mhz clock output for usb.
3 ics951601 preliminary prouct preview 0663c?10/04/05 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transf erred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte notes: controller (host) ics (slave/receiver) start bit address d3 (h) a c k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a c k dummy command code ack dummy byte count a c k byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 a c k byte 5 ack stop bit how to write:
4 ics951601 preliminary product preview 0663c?10/04/05 byte 0: functionality and frequency select register (default = 0) serial configuration command bitmap bit2 bit7 bit6 bit5 bit4 66mhz 33mhz features fs4 fs3 fs2 fs1 fs0 00000 66 33 -0.25 % down spread 00001 66 33 -0.5 % down spread 00010 66 33 -1.0 % down spread 00011 66 33 -1.5 % down spread 00100 66 33 + 0.25 % center spread 00101 66 33 + 0.5 % center spread 00110 66 33 + 1.0 % center spread 00111 66.6 33.3 + 1.5 % center spread 01000 67.32 33.66 2% over-clocking 01001 68.64 34.32 4% over-clocking 01010 6 9 . 9 6 34. 9 8 6% over-clocking 01011 72.6 36.3 10% over-clocking 01100 65.27 32.63 2% under- clocking 01101 63. 9 6 31. 9 7 2% under- clocking 01110 62.6 31.3 2% under- clocking 01111 60 30 2% under- clocking 10000 66.6 33.3 -1.4 % down spread 10001 66.6 33.3 -1.6 % down spread 10010 66.6 33.3 -1.8 % down spread 10011 66.6 33.3 -2.0 % down spread 10100 66.6 33.3 + 1.4 % center spread 10101 66.6 33.3 + 1.6 % center spread 10110 66.6 33.3 + 1.8 % center spread 10111 66.6 33.3 + 2.0 % center spread bit1 0-normal 1-spread spectrum enabled 0 bit0 0-running 1-tristate all outputs 0 bit pwd 00000 bit 2,7:4 bit3 0 0-frequency and spread is seleced by hardware select. latched input 1-frequency is seleced by bit2, 7:4
5 ics951601 preliminary prouct preview 0663c?10/04/05 byte 1: pci1a stop clocks register (1 = enable, 0 = disable) byte 2: pci2a stop clocks register (1 = enable, 0 = disable) byte 3: pci2b stop clocks register (1 = enable, 0 = disable) byte 4: reserved register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b4 21 7 _ a 1 i c p 6 t i b3 21 6 _ a 1 i c p 5 t i b0 21 5 _ a 1 i c p 4 t i b9 11 4 _ a 1 i c p 3 t i b6 11 3 _ a 1 i c p 2 t i b5 11 2 _ a 1 i c p 1 t i b2 11 1 _ a 1 i c p 0 t i b1 11 0 _ a 1 i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b 5 3 12 _ a 2 i c p 6 t i b 4 3 11 _ a 2 i c p 5 t i b 1 3 10 _ a 2 i c p 4 t i b 9 2 12 _ b 1 i c p 3 t i b 8 2 11 _ b 1 i c p 2 t i b 5 2 10 _ b 1 i c p 1 t i b - xd e v r e s e r 0 t i b - xd e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b1 41 2 _ b 2 i c p 6 t i b0 41 1 _ b 2 i c p 5 t i b7 31 0 _ b 2 i c p 4 t i b-x d e v r e s e r 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b8 41 z h m 8 4 6 t i b110 f e r 5 t i b-x d e v r e s e r 4 t i b-x d e v r e s e r 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r byte 5: latched input read back register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x b 2 l e s 6 t i b-x b 1 l e s 5 t i b-x a 2 l e s 4 t i b-x a 1 l e s 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r byte 6: reserved for byte count register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d a e r r o f d e v r e s e r t n u o c e t y b 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-0 d e v r e s e r note: pwd = power-up default
6 ics951601 preliminary product preview 0663c?10/04/05 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . 115c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; v dd, v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 5ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ma i dd3.3op100 c l = 0 pf; select @ 100 mhz 160 ma i dd3.3op133 c l = 0 pf; select @ 133 mhz 160 ma input frequency f i v dd = 3.3 v; 11 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms 1 guaranteed by design, not 100% tested in production. input capacitance 1 operating supply current electrical characteristics - input/supply/common output parameters t a = 0 - 70c; v dd = 3.3 v +/-5%; v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2. 5op100 c l = 0 pf; select @ 100 mhz 16 75 ma supply current i dd2. 5op133 c l = 0 pf; select @ 133 mhz 1 99 0ma power down supply current i dd2. 5pd c l = 0 pf; pwrdwn# = 0 0.1 100 a 1 guaranteed by design, not 100% tested in production.
7 ics951601 preliminary prouct preview 0663c?10/04/05 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 v output low voltage v ol1 i ol = 9 .4 ma 0.4 v output high current i oh1 v oh = 2.0 v -22 ma output low current i ol1 v ol = 0.8 v 16 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 2 ns duty cycle 1 d t1 v t = 1.5 v 45 55 % skew 1 t sk1 v t = 1.5 v @ 33.33 170 ps skew 1 t sk2 v t = 1.5 v @ 66.66 340 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 48 mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 4 ns duty cycle 1 d t5 v t = 1.5 v 45 55 % jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v 350 ps 1 guaranteed by design, not 100% tested in production.
8 ics951601 preliminary product preview 0663c?10/04/05 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 4 ns duty cycle 1 d t5 v t = 1.5 v 45 55 % jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v 500 ps 1 guaranteed by design, not 100% tested in production.
9 ics951601 preliminary prouct preview 0663c?10/04/05 ordering information ics951601 y flf lead free, rohs compliant (optional) pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator device type prefix ics = standard device example: ics xxxx y f - ppp lf index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .0 9 5 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .3 9 5 .420 e1 7.40 7.60 .2 9 1.2 99 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, m o-118 variations see variations see variations n d mm. d ( inch )
10 ics951601 preliminary product preview 0663c?10/04/05 revision history rev. issue date description page # c 10/4/2005 added lf to ordering information 9
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